The present invention relates to a semiconductor switch and specifically to a small, inexpensive semiconductor switch having reduced ON-resistance and excellent switching response property.
The conventional techniques of the semiconductor switch are described with reference to FIG. 6. The semiconductor switch shown in FIG. 6 includes a gray level generation circuit 400 for generating a gray level voltage, an analog switch circuit 410 and a switch control circuit 420. Any gray level voltage VM of the gray level generation circuit 400 is transmitted to an output terminal through the analog switch circuit 410.
The analog switch circuit 410 is typically formed by a P-channel MOS transistor 412 and an N-channel MOS transistor 411 connected in parallel as shown in FIG. 6. The sources and drains of the P-channel MOS transistor 412 and the N-channel MOS transistor 411 are respectively coupled together. Where the voltage which is to turn on/off the analog switch circuit 410 is supplied from the switch control circuit 420 and HIGH-level or LOW-level signal φ is connected to the gate terminal of the P-channel MOS transistor 412, signal Nφ connected to the gate terminal of the N-channel MOS transistor 411 is the inverse of signal φ as to HIGH-level and LOW-level. The backgate terminal of the N-channel MOS transistor 411, i.e., the P-well, is connected to the L-side power supply of the lowest potential, and the backgate terminal of the P-channel MOS transistor 412, i.e., the N-well, is connected to the H-side power supply of the highest potential.
In the analog switch circuit 410 having such a conventional CMOS structure, when HIGH-level voltage of signal Nφ is applied to the gate terminal of the N-channel MOS transistor 411, the N-channel MOS transistor 411 becomes conducting, while LOW-level voltage of signal φ is applied to the gate terminal of the P-channel MOS transistor 412 so that the P-channel MOS transistor 412 also becomes conducting. Therefore, the analog switch circuit 410 becomes conducting (ON) so that gray level voltage VM is transmitted to the output terminal.
Then, when LOW-level voltage of signal Nφ is applied to the gate terminal of the N-channel MOS transistor 411, the N-channel MOS transistor 411 becomes non-conducting, while HIGH-level voltage of signal φ is applied to the gate terminal of the P-channel MOS transistor 412 so that the P-channel MOS transistor 412 also becomes non-conducting. Therefore, the analog switch circuit 410 becomes non-conducting (OFF), gray level voltage VM is not transmitted to the output terminal.
If, among the voltages supplied to the P-channel MOS transistor 412, the backgate voltage is lower than the source voltage, current leakage occurs at a PN junction existing between the P-well, which is the source of the P-channel MOS transistor 412, and the N-well, which is the backgate of the P-channel MOS transistor 412. Thus, the backgate voltage of the P-channel MOS transistor 412 is preferably equal to or higher than the source voltage of the P-channel MOS transistor 412. In the conventional technique, the backgate voltage of the P-channel MOS transistor 412 is connected to the H-side power supply of the highest potential. Also in the N-channel MOS transistor 411, if among the supplied voltages the backgate voltage is higher than the source voltage, current leakage occurs at a PN junction existing between the N-well, which is the source of the N-channel MOS transistor 411, and the P-well, which is the backgate of the N-channel MOS transistor 411. Thus, the backgate voltage of the N-channel MOS transistor 411 is preferably equal to or lower than the source voltage of the N-channel MOS transistor 411. In the conventional technique, the backgate voltage of the N-channel MOS transistor 411 is connected to the L-side power supply of the lowest potential.
However, in the conventional technique, a potential difference occurs between the potential of the source electrode and the potential of the backgate electrode in each of the MOS transistors 411 and 412 of the analog switch circuit 410. Accordingly, the threshold voltage of the MOS transistors 411 and 412 increases due to substrate bias effects. The substrate bias effects are especially large when input voltage VM of the analog switch circuit 410 is an analog voltage near the midpoint potential, so that the ON-resistance of the analog switch circuit 410 is high. Near the midpoint potential, the gate-source voltage itself, which drives the gate terminal of the analog switch circuit 410, is small.
Considering that a typical MOS transistor is turned on when the potential difference between the gate and the source exceeds the threshold voltage, such a small gate-source voltage and large threshold voltage lead to a high ON-resistance, which makes signal transmission difficult. As a result, the operation speed decreases, and the error in accuracy of the voltage output from the output terminal of the analog switch circuit 410 increases. When the potential difference between the gate and source of the MOS transistors 411 and 412 does not exceed the threshold voltage, the analog switch circuit 410 does not turn on.
Solutions to the above problems are, for example, changing the size of the MOS transistors, decreasing the threshold voltage of the MOS transistors, and using depression-type MOS transistors. These solutions, however, cause an increase in current leakage and an increase in chip cost (see U.S. Pat. No. 7,038,525).
The substrate bias effects can be avoided, in a MOS transistor having a plurality of wells aligned in the depth direction, such as a triple well structure, or the like, by the source terminal and backgate terminal of a MOS transistor are coupled together to have the same potential although such an arrangement causes an increase in area of the chip.
However, even if as shown in FIG. 7 the source terminal and backgate terminal of the MOS transistor in a triple well structure are coupled together, the P-well which constitutes the backgate of the N-channel MOS transistor 411 and the N-well which surrounds the P-well form the reverse bias of PN junction, and reverse bias leakage current I3 is produced at this PN junction. As for the unshown P-channel MOS transistor 412 also, the N-well which constitutes the backgate of the P-channel MOS transistor and the P-well which surrounds the N-well form the reverse bias of PN junction, and a reverse bias leakage current is produced at the PN junction. These reverse bias leakage currents increase as the potential difference between the P- and N-phases of the PN junction increases. In miniaturization processes of recent years, larger current leakage occurs due to the substrate current and hot carriers.
Reverse bias leakage current I3 is supplied from the gray level generation circuit 400 to which the analog switch circuit 410 is connected. Although the design intends that the current flowing through the gray level generation circuit 400 desirably flow without branching from the H-side power supply to the L-side power supply (I2=I1), branching of reverse bias leakage current I3 from the gray level generation circuit 400 to the analog switch circuit 410 leads to I2=I1−I3. As a result, an error occurs in the gray level voltage due to resistive voltage division in the gray level generation circuit 400, so that accuracy in the voltage output from the output terminal of the analog switch circuit 410 deteriorates.